Synchronous Counter (Part 2) | Synchronous BCD Counter

The video script begins with an introduction to the topic of synchronous counters, specifically focusing on the design procedure for these electronic devices. It mentions a previous video that covered binary synchronous counters, which are full modulus counters that cycle through all possible output states. The script then introduces the aim of the current video, which is to design synchronous counters that count in a specific sequence, not just the binary sequence. Two examples are highlighted: designing a synchronous BCD (Binary-Coded Decimal) counter, also known as a MOD-10 counter, and designing a counter that counts in a given specific sequence. The process starts with determining the number of flip flops required for the counter, which for a BCD counter is four, to accommodate the decimal counting from 0 to 9.

This paragraph delves into the specifics of designing a synchronous BCD counter using JK flip flops. It explains the process of creating a state diagram to illustrate the counting sequence from 0 to 9 and addresses the 'don't care' terms for the remaining input combinations. The excitation table for the JK flip flop is introduced as a necessary reference for designing the counter's excitation table. The paragraph outlines the steps to determine the excitation inputs for each flip flop, using the JK flip flop's excitation table to find the correct J and K inputs for transitions between states. The goal is to create a counter that can count in decimal from 0 to 9 and then reset, which requires careful selection of excitation inputs to ensure accurate counting.

The script continues with the process of finding minimal expressions for the inputs of each flip flop in the synchronous BCD counter. It describes using a K-map to simplify the excitation inputs for J3 and K3, considering both the valid and 'don't care' input combinations. The minimal expressions for J3 and K3 are determined to be related to the outputs Q2, Q1, and Q0. The process is then repeated for J2, K2, J1, K1, J0, and K0 inputs, with the goal of simplifying the logic to create a more efficient circuit. The minimal expressions help in reducing the complexity and potential errors in the counter's design, making it easier to implement and troubleshoot.

The script discusses the importance of checking for the lockout condition in synchronous counters. It explains that counters are not designed to go through all possible states, and some states may be unused or invalid. The lockout condition occurs if the counter gets stuck in an unused state and cannot return to a valid state within a few clock cycles. The script describes how to create a table to check if the counter can transition out of invalid states, using the present state and inputs to determine the next state. The example given shows that the BCD counter is self-correcting, meaning it can automatically return to a valid state from an unused state, which is a desirable feature in counter design.

This paragraph introduces the design of a counter that does not follow a binary counting sequence but rather counts in a specific sequence: 0, 3, 5, and 6, then repeats. The script explains that the method used for binary counting cannot be applied here due to the non-standard sequence. Instead, the maximum count in the sequence is considered to determine the number of flip flops required, which in this case is three. The paragraph outlines the steps for drawing the state diagram for this counter, taking into account the valid and 'don't care' states, and the use of T flip flops for the design. The excitation table for the T flip flop is used to find the required inputs for each flip flop to achieve the desired counting sequence.

The script addresses the issue of designing a counter that is not self-correcting and requires modification to avoid the lockout condition. It explains that if a counter cannot exit an invalid state on its own, it needs to be modified to ensure it can reset to a valid state. The example given outlines the process of finding the next state for each invalid state and determining the conditions under which a reset pulse should be generated to return the counter to the initial state. The logical expression for the reset input is derived using a K-map and Boolean algebra, and a method to apply this reset input to the clear input of each flip flop is provided. The modification ensures that the counter can always reset itself and avoid getting stuck in an invalid state.

The final paragraph of the script wraps up the discussion on designing synchronous counters with specific counting sequences. It summarizes the process covered in the video, which includes determining the number of flip flops, drawing state diagrams, selecting flip flop types, creating excitation tables, finding minimal expressions, and modifying the design to avoid lockout conditions. The script encourages viewers to ask questions or provide suggestions in the comments section and to like and subscribe for more educational content on similar topics.